Manufacturing
A fab network built on copy-exactly discipline: the same tools, the same recipes, the same result — in Chicago, Dresden, Chandler, and Singapore.
1.4M
Wafer starts per year
300mm equivalent across the network
99.2%
Automated lot moves
Lights-out overhead transport
310K
m² of cleanroom
ISO Class 1–5, five sites
<0.07
Defects per cm²
D0 on mature SG5 flow
Fab network
Geographically resilient capacity with dedicated corridors for leading-edge, automotive, and specialty demand.
Our flagship campus and the largest semiconductor facility in North America: 140,000 m² of ISO Class 1 cleanroom, fully EUV-equipped, running lights-out automation across 99.2% of lot moves.
The heart of our European automotive supply chain, co-located with customer failure-analysis labs and qualified to VDA 6.3. Zero-defect methodology with full lot genealogy.
Our Southwest hub, serving hyperscaler and networking customers with dedicated capacity corridors and CHIPS-aligned domestic supply guarantees.
A second Chicago megasite adding SG2 capacity and our first co-located advanced packaging line, connecting front-end and 3D assembly under one roof.
Specialty technologies for RF front-ends, silicon photonics, and BCD power — close to the OSAT ecosystem of Southeast Asia.
Quality & yield
Every claim — in a press release or a process recipe — must survive contact with the wafer map. Four disciplines make that possible.
Every tool, recipe, and environmental parameter is replicated across sites to the second decimal, so a design qualified in Chicago ships identically from Chandler.
Inline metrology feeds a fleet of defect-classification models that flag excursions within minutes, compressing yield ramps by up to 40% versus prior nodes.
From ingot to package, every die carries a cryptographic trace of its process history — the foundation of our automotive and aerospace qualifications.
Overhead transport and schedule optimization move 99.2% of lots without human touch, cutting cycle-time variability and human-particle contamination.