SWARGATE
Researchers working in a semiconductor laboratory

Innovation & R&D

The road to 1.4 nanometers is paved here

Device research, lithography, packaging, and materials science under one roadmap — so the next node is a schedule, not a bet.

$4.2B

Annual R&D investment

11% of revenue, FY2026

9,400+

Patents granted

1,700 filed in the last year

2,900

R&D engineers

Across Chicago, Dresden, and Chandler

2

High-NA EUV scanners

Installed in the Chicago R&D line

Research programs

Six bets on the next decade of scaling

Each program is staffed to production intent — with pilot-line silicon, not slideware, as the exit criterion.

1.4NM-CLASS

SG14 pathfinding

Complementary FET (CFET) device research with our consortium partners, targeting risk production in the early 2030s. Vertically stacked n/p devices promise another full node of density scaling.

POWERVIA-CLASS PDN

Backside power delivery

Moving the power delivery network to the wafer backside frees routing tracks and cuts IR droop by up to 30%. Debuting on SG2, extended to buried rail on SG14.

0.55 NA LITHOGRAPHY

High-NA EUV insertion

Two High-NA EUV scanners are installed in the Chicago R&D line, printing sub-20nm pitches in a single exposure and retiring the most complex multi-patterning flows.

UCIE-NATIVE

Chiplet ecosystem

A UCIe-native die-to-die IP portfolio, known-good-die test methodology, and an open chiplet marketplace with 30+ ecosystem partners.

CO-PACKAGED OPTICS

Silicon photonics

Optical I/O co-packaged with switch and accelerator silicon — 5× the bandwidth density of copper at a third of the pJ/bit.

EXPLORATORY

Cryogenic & quantum

Cryo-CMOS control silicon for quantum processors, developed with national laboratories and university partners in three countries.

Ecosystem

Research is a team sport

Joint labs, sponsored fellowships, and shared pilot-line access with six research universities — plus the imec and SEMATECH-successor consortia.

  • University of Illinois Urbana-Champaign
  • Purdue University
  • TU Dresden
  • Arizona State University
  • NTU Singapore
  • EPFL Lausanne

The Semiconductor Scholars program commits $150M to train 25,000 engineers by 2030 — funding cleanroom teaching labs, fellowships, and faculty chairs at partner institutions.

Join the R&D organization →